MT41K128M16JT-125 M:K

2Gb: x4, x8, x16 DDR3L SDRAM Description DDR3L SDRAM MT41K512M4 – 64 Meg x 4 x 8 banks MT41K256M8 – 32 Meg x 8 x 8 banks MT41K128M16 – 16 Meg x 16 x 8 banks Description • • • • The 1.35V DDR3L SDRAM device is a low-voltage version of the 1.5V DDR3 SDRAM device. Refer to the DDR3 (1.5V) SDRAM data sheet specifications when running in 1.5V compatible mode. Options • • • • • • • • Marking • Configuration – 512 Meg x 4 – 256 Meg x 8 – 128 Meg x 16 • FBGA package (Pb-free) – x4, x8 – 78-ball (8mm x 10.5mm x 1.2mm) Rev. K • FBGA package (Pb-free) – x16 – 96-ball (8mm x 14mm x 1.2mm) Rev. K • Timing – cycle time – 1.07ns @ CL = 13 (DDR3-1866) – 1.25ns @ CL = 11 (DDR3-1600) – 1.5ns @ CL = 9 (DDR3-1333) – 1.875ns @ CL = 7 (DDR3-1066) • Operating temperature – Commercial (0°C ≤ T C ≤ +95°C) – Industrial (–40°C ≤ T C ≤ +95°C) • Revision Features • • • • • • • Automatic self refresh (ASR) Write leveling Multipurpose register Output driver calibration VDD = V DDQ = 1.35V (1.283–1.45V) Backward-compatible to V DD = V DDQ = 1.5V ±0.075V Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS (READ) latency (CL) Programmable posted CAS additive latency (AL) Programmable CAS (WRITE) latency (CWL) Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Self refresh mode TC of 95°C – 64ms, 8192-cycle refresh up to 85°C – 32ms, 8192-cycle refresh at >85°C to 95°C Self refresh temperature (SRT) 512M4 256M8 128M16 DA JT -107 -125 -15E -187E None IT :K Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL -1071, 2, 3 1866 13-13-13 13.91 13.91 13.91 -1251, 2 1600 11-11-11 13.75 13.75 13.75 -15E1 1333 9-9-9 13.5 13.5 13.5 -187E 1066 7-7-7 13.1 13.1 13.1 Notes: tRCD (ns) tRP (ns) CL (ns) 1. Backward compatible to 1066, CL = 7 (-187E). 2. Backward compatible to 1333, CL = 9 (-15E). 3. Backward compatible to 1600, CL = 11 (-125). CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 2Gb: x4, x8, x16 DDR3L SDRAM Description Table 2: Addressing Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16 Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks Refresh count 8K 8K 8K 32K A[14:0] 32K A[14:0] 16K A[13:0] Row address Bank address Column address 8 BA[2:0] 8 BA[2:0] 8 BA[2:0] 2K A[11, 9:0] 1K A[9:0] 1K A[9:0] Figure 1: DDR3L Part Numbers Example Part Number: MT41K256M8DA-107:K - Configuration Package Speed Revision { MT41K : :K Revision Configuration 512 Meg x 4 512M4 Temperature 256 Meg x 8 256M8 Commercial 128 Meg x 16 128M16 Industrial temperature Package 78-ball 8mm x 10.5mm FBGA DA -107 96-ball 8mm x 14mm FBGA JT -125 -15E -187E Note: None IT Speed Grade tCK = 1.071ns, CL = 13 tCK = 1.25ns, CL = 11 tCK = 1.5ns, CL = 9 tCK = 1.87ns, CL = 7 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Description Contents Important Notes and Warnings ....................................................................................................................... 12 State Diagram ................................................................................................................................................ 13 Functional Description ................................................................................................................................... 14 Industrial Temperature ............................................................................................................................... 14 General Notes ............................................................................................................................................ 14 Functional Block Diagrams ............................................................................................................................. 16 Ball Assignments and Descriptions ................................................................................................................. 18 Package Dimensions ....................................................................................................................................... 24 Electrical Specifications .................................................................................................................................. 26 Thermal Characteristics .................................................................................................................................. 38 Electrical Specifications – IDD Specifications and Conditions ............................................................................ 40 Electrical Characteristics – IDD Specifications .................................................................................................. 51 Electrical Specifications – DC and AC .............................................................................................................. 52 DC Operating Conditions ........................................................................................................................... 52 Input Operating Conditions ........................................................................................................................ 53 DDR3L 1.35V AC Overshoot/Undershoot Specification ................................................................................ 57 DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals .............................................................. 61 DDR3L 1.35V Slew Rate Definitions for Differential Input Signals ................................................................. 63 ODT Characteristics ....................................................................................................................................... 64 1.35V ODT Resistors ................................................................................................................................... 65 ODT Sensitivity .......................................................................................................................................... 66 ODT Timing Definitions ............................................................................................................................. 66 Output Driver Impedance ............................................................................................................................... 70 34 Ohm Output Driver Impedance .............................................................................................................. 71 DDR3L 34 Ohm Driver ................................................................................................................................ 72 DDR3L 34 Ohm Output Driver Sensitivity .................................................................................................... 73 DDR3L Alternative 40 Ohm Driver ............................................................................................................... 74 DDR3L 40 Ohm Output Driver Sensitivity .................................................................................................... 74 Output Characteristics and Operating Conditions ............................................................................................ 76 Reference Output Load ............................................................................................................................... 79 Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 79 Slew Rate Definitions for Differential Output Signals .................................................................................... 81 Speed Bin Tables ............................................................................................................................................ 82 Electrical Characteristics and AC Operating Conditions ................................................................................... 86 Command and Address Setup, Hold, and Derating .......................................................................................... 104 Data Setup, Hold, and Derating ...................................................................................................................... 111 Commands – Truth Tables ............................................................................................................................. 120 Commands ................................................................................................................................................... 123 DESELECT ................................................................................................................................................ 123 NO OPERATION ........................................................................................................................................ 123 ZQ CALIBRATION LONG ........................................................................................................................... 123 ZQ CALIBRATION SHORT .......................................................................................................................... 123 ACTIVATE ................................................................................................................................................. 123 READ ........................................................................................................................................................ 123 WRITE ...................................................................................................................................................... 124 PRECHARGE ............................................................................................................................................. 125 REFRESH .................................................................................................................................................. 125 SELF REFRESH .......................................................................................................................................... 126 DLL Disable Mode ..................................................................................................................................... 127 Input Clock Frequency Change ...................................................................................................................... 131 CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Description Write Leveling ............................................................................................................................................... 133 Write Leveling Procedure ........................................................................................................................... 135 Write Leveling Mode Exit Procedure ........................................................................................................... 137 Initialization ................................................................................................................................................. 138 Voltage Initialization/Change ........................................................................................................................ 140 VDD Voltage Switching ............................................................................................................................... 141 Mode Registers .............................................................................................................................................. 142 Mode Register 0 (MR0) ................................................................................................................................... 143 Burst Length ............................................................................................................................................. 143 Burst Type ................................................................................................................................................. 144 DLL RESET ................................................................................................................................................ 145 Write Recovery .......................................................................................................................................... 146 Precharge Power-Down (Precharge PD) ...................................................................................................... 146 CAS Latency (CL) ....................................................................................................................................... 146 Mode Register 1 (MR1) ................................................................................................................................... 148 DLL ENABLE/DISABLE .............................................................................................................................. 148 Output Drive Strength ............................................................................................................................... 149 OUTPUT ENABLE/DISABLE ...................................................................................................................... 149 TDQS ENABLE .......................................................................................................................................... 149 On-Die Termination (ODT) ........................................................................................................................ 150 WRITE LEVELING ..................................................................................................................................... 150 Posted CAS Additive Latency (AL) ............................................................................................................... 150 Mode Register 2 (MR2) ................................................................................................................................... 152 CAS WRITE Latency (CWL) ........................................................................................................................ 152 AUTO SELF REFRESH (ASR) ....................................................................................................................... 153 SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 153 SRT versus ASR .......................................................................................................................................... 154 Dynamic On-Die Termination (ODT) ......................................................................................................... 154 Mode Register 3 (MR3) ................................................................................................................................... 155 MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 155 MPR Functional Description ...................................................................................................................... 156 MPR Address Definitions and Bursting Order .............................................................................................. 157 MPR Read Predefined Pattern .................................................................................................................... 162 MODE REGISTER SET (MRS) Command ........................................................................................................ 162 ZQ CALIBRATION Operation ......................................................................................................................... 163 ACTIVATE Operation ..................................................................................................................................... 164 READ Operation ............................................................................................................................................ 166 WRITE Operation .......................................................................................................................................... 177 DQ Input Timing ....................................................................................................................................... 185 PRECHARGE Operation ................................................................................................................................. 187 SELF REFRESH Operation .............................................................................................................................. 187 Extended Temperature Usage ........................................................................................................................ 189 Power-Down Mode ........................................................................................................................................ 190 RESET Operation ........................................................................................................................................... 198 On-Die Termination (ODT) ............................................................................................................................ 200 Functional Representation of ODT ............................................................................................................. 200 Nominal ODT ............................................................................................................................................ 200 Dynamic ODT ............................................................................................................................................... 202 Dynamic ODT Special Use Case ................................................................................................................. 202 Functional Description .............................................................................................................................. 202 Synchronous ODT Mode ................................................................................................................................ 208 ODT Latency and Posted ODT .................................................................................................................... 208 CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Description Timing Parameters .................................................................................................................................... 208 ODT Off During READs .............................................................................................................................. 211 Asynchronous ODT Mode .............................................................................................................................. 213 Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 215 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 217 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 219 CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Description List of Figures Figure 1: DDR3L Part Numbers ........................................................................................................................ 2 Figure 2: Simplified State Diagram ................................................................................................................. 13 Figure 3: 512 Meg x 4 Functional Block Diagram ............................................................................................. 16 Figure 4: 256 Meg x 8 Functional Block Diagram ............................................................................................. 17 Figure 5: 128 Meg x 16 Functional Block Diagram ........................................................................................... 17 Figure 6: 78-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 18 Figure 7: 96-Ball FBGA – x16 Ball Assignments (Top View) ............................................................................... 19 Figure 8: 78-Ball FBGA – x4, x8 (DA) ............................................................................................................... 24 Figure 9: 96-Ball FBGA – x16 (JT) ................................................................................................................... 25 Figure 10: Thermal Measurement Point ......................................................................................................... 39 Figure 11: DDR3L 1.35V Input Signal .............................................................................................................. 56 Figure 12: Overshoot ..................................................................................................................................... 57 Figure 13: Undershoot ................................................................................................................................... 58 Figure 14: V IX for Differential Signals .............................................................................................................. 59 Figure 15: Single-Ended Requirements for Differential Signals ........................................................................ 59 Figure 16: Definition of Differential AC-Swing and tDVAC ............................................................................... 60 Figure 17: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 62 Figure 18: DDR3L 1.35V Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .............. 63 Figure 19: ODT Levels and I-V Characteristics ................................................................................................ 64 Figure 20: ODT Timing Reference Load .......................................................................................................... 67 Figure 21: tAON and tAOF Definitions ............................................................................................................ 68 Figure 22: tAONPD and tAOFPD Definitions ................................................................................................... 68 Figure 23: tADC Definition ............................................................................................................................. 69 Figure 24: Output Driver ................................................................................................................................ 70 Figure 25: DQ Output Signal .......................................................................................................................... 77 Figure 26: Differential Output Signal .............................................................................................................. 78 Figure 27: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 79 Figure 28: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 80 Figure 29: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 81 Figure 30: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 107 Figure 31: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 108 Figure 32: Tangent Line for tIS (Command and Address – Clock) .................................................................... 109 Figure 33: Tangent Line for tIH (Command and Address – Clock) .................................................................... 110 Figure 34: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 116 Figure 35: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 117 Figure 36: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 118 Figure 37: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 119 Figure 38: Refresh Mode ............................................................................................................................... 126 Figure 39: DLL Enable Mode to DLL Disable Mode ........................................................................................ 128 Figure 40: DLL Disable Mode to DLL Enable Mode ........................................................................................ 129 Figure 41: DLL Disable tDQSCK .................................................................................................................... 130 Figure 42: Change Frequency During Precharge Power-Down ........................................................................ 132 Figure 43: Write Leveling Concept ................................................................................................................. 133 Figure 44: Write Leveling Sequence ............................................................................................................... 136 Figure 45: Write Leveling Exit Procedure ....................................................................................................... 137 Figure 46: Initialization Sequence ................................................................................................................. 139 Figure 47: V DD Voltage Switching .................................................................................................................. 141 Figure 48: MRS to MRS Command Timing ( tMRD) ......................................................................................... 142 Figure 49: MRS to nonMRS Command Timing ( tMOD) .................................................................................. 143 Figure 50: Mode Register 0 (MR0) Definitions ................................................................................................ 144 CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Description Figure 51: READ Latency .............................................................................................................................. 147 Figure 52: Mode Register 1 (MR1) Definition ................................................................................................. 148 Figure 53: READ Latency (AL = 5, CL = 6) ....................................................................................................... 151 Figure 54: Mode Register 2 (MR2) Definition ................................................................................................. 152 Figure 55: CAS WRITE Latency ...................................................................................................................... 153 Figure 56: Mode Register 3 (MR3) Definition ................................................................................................. 155 Figure 57: MPR Block Diagram ...................................................................................................................... 156 Figure 58: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 158 Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 159 Figure 60: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 160 Figure 61: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 161 Figure 62: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 163 Figure 63: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 164 Figure 64: Example: tFAW ............................................................................................................................. 165 Figure 65: READ Latency .............................................................................................................................. 166 Figure 66: Consecutive READ Bursts (BL8) .................................................................................................... 168 Figure 67: Consecutive READ Bursts (BC4) .................................................................................................... 168 Figure 68: Nonconsecutive READ Bursts ....................................................................................................... 169 Figure 69: READ (BL8) to WRITE (BL8) .......................................................................................................... 169 Figure 70: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 170 Figure 71: READ to PRECHARGE (BL8) .......................................................................................................... 170 Figure 72: READ to PRECHARGE (BC4) ......................................................................................................... 171 Figure 73: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 171 Figure 74: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 171 Figure 75: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 173 Figure 76: Data Strobe Timing – READs ......................................................................................................... 174 Figure 77: Method for Calculating tLZ and tHZ ............................................................................................... 175 Figure 78: tRPRE Timing ............................................................................................................................... 175 Figure 79: tRPST Timing ............................................................................................................................... 176 Figure 80: tWPRE Timing .............................................................................................................................. 178 Figure 81: tWPST Timing .............................................................................................................................. 178 Figure 82: WRITE Burst ................................................................................................................................ 179 Figure 83: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 180 Figure 84: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 180 Figure 85: Nonconsecutive WRITE to WRITE ................................................................................................. 181 Figure 86: WRITE (BL8) to READ (BL8) .......................................................................................................... 181 Figure 87: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 182 Figure 88: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 183 Figure 89: WRITE (BL8) to PRECHARGE ........................................................................................................ 184 Figure 90: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 184 Figure 91: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 185 Figure 92: Data Input Timing ........................................................................................................................ 186 Figure 93: Self Refresh Entry/Exit Timing ...................................................................................................... 188 Figure 94: Active Power-Down Entry and Exit ................................................................................................ 192 Figure 95: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 192 Figure 96: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 193 Figure 97: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 193 Figure 98: Power-Down Entry After WRITE .................................................................................................... 194 Figure 99: Power-Down Entry After WRITE with Auto Precharge (WRAP) ........................................................ 194 Figure 100: REFRESH to Power-Down Entry .................................................................................................. 195 Figure 101: ACTIVATE to Power-Down Entry ................................................................................................. 195 Figure 102: PRECHARGE to Power-Down Entry ............................................................................................. 196 CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Description Figure 103: Figure 104: Figure 105: Figure 106: Figure 107: Figure 108: Figure 109: Figure 110: Figure 111: Figure 112: Figure 113: Figure 114: Figure 115: Figure 116: Figure 117: Figure 118: Figure 119: MRS Command to Power-Down Entry ......................................................................................... 196 Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 197 RESET Sequence ......................................................................................................................... 199 On-Die Termination ................................................................................................................... 200 Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 205 Dynamic ODT: Without WRITE Command .................................................................................. 205 Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 206 Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 207 Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 207 Synchronous ODT ...................................................................................................................... 209 Synchronous ODT (BC4) ............................................................................................................. 210 ODT During READs .................................................................................................................... 212 Asynchronous ODT Timing with Fast ODT Transition .................................................................. 214 Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 216 Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 218 Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 220 Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 220 CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Description List of Tables Table 1: Key Timing Parameters ....................................................................................................................... 1 Table 2: Addressing ......................................................................................................................................... 2 Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 20 Table 4: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 22 Table 5: Input/Output Capacitance ................................................................................................................ 26 Table 6: DC Electrical Characteristics and Operating Conditions – 1.35V Operation ......................................... 26 Table 7: DC Electrical Characteristics and Operating Conditions – 1.5V Operation ........................................... 26 Table 8: Input Switching Conditions – Command and Address ........................................................................ 27 Table 9: Input Switching Conditions – DQ and DM ......................................................................................... 27 Table 10: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .................................................. 28 Table 11: Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ...................... 28 Table 12: RTT Effective Impedance ................................................................................................................. 29 Table 13: Reference Settings for ODT Timing Measurements ........................................................................... 30 Table 14: 34Ω Driver Impedance Characteristics ............................................................................................. 30 Table 15: 40Ω Driver Impedance Characteristics ............................................................................................. 30 Table 16: Single-Ended Output Driver Characteristics ..................................................................................... 31 Table 17: Differential Output Driver Characteristics ........................................................................................ 31 Table 18: Electrical Characteristics and AC Operating Conditions .................................................................... 31 Table 19: Derating Values for tIS/tIH – AC160/DC90-Based .............................................................................. 32 Table 20: Derating Values for tIS/tIH – AC135/DC90-Based .............................................................................. 33 Table 21: Derating Values for tIS/tIH – AC125/DC90-Based .............................................................................. 33 Table 22: Minimum Required Time tVAC Above V IH(AC) (Below V IL[AC]) for Valid ADD/CMD Transition .............. 34 Table 23: Derating Values for tDS/tDH – AC160/DC90-Based ........................................................................... 34 Table 24: Derating Values for tDS/tDH – AC135/DC90-Based ........................................................................... 35 Table 25: Derating Values for tDS/tDH – AC130/DC100-Based at 2V/ns ............................................................ 36 Table 26: Minimum Required Time tVAC Above V IH(AC) (Below V IL(AC)) for Valid DQ Transition .......................... 37 Table 27: Thermal Characteristics .................................................................................................................. 38 Table 28: Thermal Impedance ........................................................................................................................ 39 Table 29: DDR3L Timing Parameters Used for I DD Measurements – Clock Units ............................................... 40 Table 30: DDR3L IDD0 Measurement Loop ...................................................................................................... 41 Table 31: DDR3L IDD1 Measurement Loop ...................................................................................................... 42 Table 32: DDR3L IDD Measurement Conditions for Power-Down Currents ....................................................... 43 Table 33: DDR3L IDD2N and IDD3N Measurement Loop .................................................................................... 44 Table 34: DDR3L IDD2NT Measurement Loop .................................................................................................. 44 Table 35: DDR3L IDD4R Measurement Loop .................................................................................................... 45 Table 36: DDR3L IDD4W Measurement Loop .................................................................................................... 46 Table 37: DDR3L IDD5B Measurement Loop .................................................................................................... 47 Table 38: DDR3L IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 ........................................................ 48 Table 39: DDR3L IDD7 Measurement Loop ...................................................................................................... 49 Table 40: IDD Maximum Limits – Die Rev. K .................................................................................................... 51 Table 41: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions .............................................. 52 Table 42: DDR3L 1.35V DC Electrical Characteristics and Input Conditions ..................................................... 53 Table 43: DDR3L 1.35V Input Switching Conditions - Command and Address .................................................. 54 Table 44: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .............................. 55 Table 45: DDR3L Control and Address Pins ..................................................................................................... 57 Table 46: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins ............................................................................. 57 Table 47: DDR3L 1.35V - Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback ... 60 Table 48: Single-Ended Input Slew Rate Definition .......................................................................................... 61 Table 49: DDR3L 1.35V Differential Input Slew Rate Definition ........................................................................ 63 Table 50: On-Die Termination DC Electrical Characteristics ............................................................................ 64 CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Description Table 51: 1.35V RTT Effective Impedance ........................................................................................................ 65 Table 52: ODT Sensitivity Definition .............................................................................................................. 66 Table 53: ODT Temperature and Voltage Sensitivity ........................................................................................ 66 Table 54: ODT Timing Definitions .................................................................................................................. 67 Table 55: DDR3L(1.35V) Reference Settings for ODT Timing Measurements .................................................... 67 Table 56: DDR3L 34 Ohm Driver Impedance Characteristics ........................................................................... 71 Table 57: DDR3L 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ........................................... 72 Table 58: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.35V ..................................... 72 Table 59: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.45V ..................................... 72 Table 60: DDR3L 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = DDR3L@1.283 ..................................... 73 Table 61: DDR3L 34 Ohm Output Driver Sensitivity Definition ........................................................................ 73 Table 62: DDR3L 34 Ohm Output Driver Voltage and Temperature Sensitivity .................................................. 73 Table 63: DDR3L 40 Ohm Driver Impedance Characteristics ........................................................................... 74 Table 64: DDR3L 40 Ohm Output Driver Sensitivity Definition ........................................................................ 74 Table 65: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 75 Table 66: DDR3L Single-Ended Output Driver Characteristics ......................................................................... 76 Table 67: DDR3L Differential Output Driver Characteristics ............................................................................ 77 Table 68: DDR3L Differential Output Driver Characteristics V OX(AC) ................................................................. 78 Table 69: Single-Ended Output Slew Rate Definition ....................................................................................... 79 Table 70: Differential Output Slew Rate Definition .......................................................................................... 81 Table 71: DDR3L-1066 Speed Bins .................................................................................................................. 82 Table 72: DDR3L-1333 Speed Bins .................................................................................................................. 83 Table 73: DDR3L-1600 Speed Bins .................................................................................................................. 84 Table 74: DDR3L-1866 Speed Bins .................................................................................................................. 85 Table 75: Electrical Characteristics and AC Operating Conditions .................................................................... 86 Table 76: Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 96 Table 77: DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based ............... 105 Table 78: DDR3L-800/1066/1333/1600 Derating Values for tIS/tIH – AC160/DC90-Based ................................ 105 Table 79: DDR3L-800/1066/1333/1600 Derating Values for tIS/tIH – AC135/DC90-Based ................................ 105 Table 80: DDR3L-1866 Derating Values for tIS/tIH – AC125/DC90-Based ........................................................ 106 Table 81: DDR3L Minimum Required Time tVAC Above V IH(AC) (Below V IL[AC]) for Valid ADD/CMD Transition . 106 Table 82: DDR3L Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ....................... 112 Table 83: DDR3L Derating Values for tDS/tDH – AC160/DC90-Based .............................................................. 112 Table 84: DDR3L Derating Values for tDS/tDH – AC135/DC100-Based ............................................................ 112 Table 85: DDR3L Derating Values for tDS/tDH – AC130/DC100-Based at 2V/ns ............................................... 114 Table 86: DDR3L Minimum Required Time tVAC Above V IH(AC) (Below V IL(AC)) for Valid DQ Transition ............. 115 Table 87: Truth Table – Command ................................................................................................................. 120 Table 88: Truth Table – CKE .......................................................................................................................... 122 Table 89: READ Command Summary ............................................................................................................ 124 Table 90: WRITE Command Summary .......................................................................................................... 124 Table 91: READ Electrical Characteristics, DLL Disable Mode ......................................................................... 130 Table 92: Write Leveling Matrix ..................................................................................................................... 134 Table 93: Burst Order .................................................................................................................................... 145 Table 94: MPR Functional Description of MR3 Bits ........................................................................................ 156 Table 95: MPR Readouts and Burst Order Bit Mapping ................................................................................... 157 Table 96: Self Refresh Temperature and Auto Self Refresh Description ............................................................ 189 Table 97: Self Refresh Mode Summary ........................................................................................................... 189 Table 98: Command to Power-Down Entry Parameters .................................................................................. 190 Table 99: Power-Down Modes ....................................................................................................................... 191 Table 100: Truth Table – ODT (Nominal) ........................................................................................................ 201 Table 101: ODT Parameters .......................................................................................................................... 201 Table 102: Write Leveling with Dynamic ODT Special Case ............................................................................. 202 CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Description Table 103: Table 104: Table 105: Table 106: Table 107: Table 108: Table 109: Dynamic ODT Specific Parameters ............................................................................................... 203 Mode Registers for RTT,nom ............................................................................................................ 203 Mode Registers for RTT(WR) ............................................................................................................ 204 Timing Diagrams for Dynamic ODT .............................................................................................. 204 Synchronous ODT Parameters ...................................................................................................... 209 Asynchronous ODT Timing Parameters for All Speed Bins .............................................................. 214 ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period ................................. 216 CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM State Diagram State Diagram Figure 2: Simplified State Diagram CKE L Power applied Power on MRS, MPR, write leveling Initialization Reset procedure SRE ZQCL From any state RESET ZQ calibration Self refresh MRS SRX REF ZQCL/ZQCS Refreshing Idle PDE ACT PDX Active powerdown Precharge powerdown Activating PDX CKE L CKE L PDE Bank active WRITE WRITE READ WRITE AP Writing READ READ AP READ WRITE WRITE AP Reading READ AP WRITE AP READ AP PRE, PREA Writing PRE, PREA PRE, PREA Precharging Reading Automatic sequence Command sequence ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 13 SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Functional Description Functional Description DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. Industrial Temperature The industrial temperature (IT) device requires that the case temperature not exceed –40°C or 95°C. JEDEC specifications require the refresh rate to double when T C exceeds 85°C; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when T C is < 0°C or >95°C. General Notes • The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation). • Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. • The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise. CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Functional Description • Complete functionality may be described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. • Any specific requirement takes precedence over a general statement. • Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation. • Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4, x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4, x8). • Dynamic ODT has a special use case: when DDR3 devices are architected for use in a single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer to the Dynamic ODT Special Use Case section. • A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be used, use the lower byte for data transfers and terminate the upper byte as noted: – – – – Connect UDQS to ground via 1kΩ* resistor. Connect UDQS# to V DD via 1kΩ* resistor. Connect UDM to V DD via 1kΩ* resistor. Connect DQ[15:8] individually to either V SS, V DD, or V REF via 1kΩ resistors,* or float DQ[15:8]. *If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT. CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Functional Block Diagrams Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM. Figure 3: 512 Meg x 4 Functional Block Diagram ODT control ODT ZQ RZQ ZQ CAL RESET# ZQCL, ZQCS CKE VSSQ To pullup/pulldown networks Control logic A12 CK, CK# VDDQ/2 BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh counter 18 15 Rowaddress MUX 15 15 Bank 0 rowaddress 32,768 latch and decoder Columns 0, 1, and 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 RTT,nom CK,CK# DLL Bank 0 memory array (32,768 x 256 x 32) 32 READ FIFO and data MUX 4 (1 . . . 4) DQ[3:0] READ drivers VDDQ/2 32 8,192 BC4 BC4 OTF I/O gating DM mask logic 3 18 Address register 3 Bank control logic (1, 2) 32 Data interface 4 Data WRITE drivers and input logic 8 DQS, DQS# VDDQ/2 RTT,nom SW1 RTT(WR) SW2 DM 3 Columns 0, 1, and 2 CK,CK# CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN RTT(WR) SW2 SW1 Column decoder Columnaddress counter/ latch RTT,nom DM 256 (x32) 11 DQ[3:0] DQS, DQS# Sense amplifiers A[14:0] BA[2:0] RTT(WR) SW2 SW1 16 Column 2 (select upper or lower nibble for BC4) Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Functional Block Diagrams Figure 4: 256 Meg x 8 Functional Block Diagram ODT control ODT ZQ RESET# RZQ Control logic CKE VSSQ To ODT/output drivers ZQ CAL A12 ZQCL, ZQCS CK, CK# VDDQ/2 BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh counter 15 Rowaddress MUX 18 15 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank control logic 3 (1 . . . 8) 8 DQ[7:0] DQS, DQS# VDDQ/2 BC4 BC4 OTF RTT,nom SW1 RTT(WR) SW2 (1, 2) (128 x64) 64 8 Data interface Data Column decoder Columnaddress counter/ latch 10 TDQS# DQ[7:0] Read drivers I/O gating DM mask logic 3 Address register SW2 DQ8 READ FIFO and data MUX 64 8,192 18 CK, CK# DLL 64 Sense amplifiers A[14:0] BA[2:0] RTT(WR) RTT,nom SW1 Bank 0 Memory array (32,768 x 128 x 64) Bank 0 rowaddress 32,768 latch and decoder 15 Columns 0, 1, and 2 VDDQ/2 Write drivers and input logic RTT,nom SW1 RTT(WR) SW2 7 3 DQS/DQS# DM/TDQS (shared pin) Columns 0, 1, and 2 CK, CK# Column 2 (select upper or lower nibble for BC4) Figure 5: 128 Meg x 16 Functional Block Diagram ODT control ODT ZQ RZQ ZQ CAL RESET# Control logic CKE VSSQ To ODT/output drivers ZQCL, ZQCS A12 CK, CK# VDDQ/2 BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh counter 17 13 Rowaddress MUX 14 14 Bank 0 rowaddress latch and decoder 16,384 RTT,nom Column 0, 1, and 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 CK, CK# DLL (1 . . . 16) Bank 0 memory array (16,384 x 128 x 128) 128 READ FIFO and data MUX 16 DQ[15:0] READ drivers LDQS, LDQS#, UDQS, UDQS# A[13:0] BA[2:0] 17 Address register 3 BC4 128 16,384 Data interface 16 Data WRITE drivers and input logic 7 3 UDQS, UDQS# VDDQ/2 128 RTT,nom SW1 RTT(WR) SW2 (1, 2) LDM/UDM Columns 0, 1, and 2 CK, CK# CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN SW2 LDQS, LDQS# Column decoder 10 RTT(WR) (1 . . . 4) (128 x128) Columnaddress counter/ latch RTT,nom SW1 BC4 OTF I/O gating DM mask logic Bank control logic DQ[15:0] VDDQ/2 Sense amplifiers 3 RTT(WR) SW2 SW1 17 Column 2 (select upper or lower nibble for BC4) Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 6: 78-Ball FBGA – x4, x8 Ball Assignments (Top View) 1 2 3 VSS VDD VSS VDDQ 4 5 6 7 8 9 NC NF, NF/TDQS# VSS VDD VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ NF, DQ6 DQS# VDD VSS VSSQ A B C D VSSQ E VREFDQ NF, DQ7 NF, DQ5 VDDQ NF, DQ4 VDDQ F NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 A14 A8 VSS G H J K L M N Notes: CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 1. Ball descriptions listed in Table 3 (page 20) are listed as “x4, x8” if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3). 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Figure 7: 96-Ball FBGA – x16 Ball Assignments (Top View) A B 1 2 3 VDDQ DQ13 VSSQ 4 5 6 7 8 9 DQ15 DQ12 VDDQ VSS VDD VSS UDQS# DQ14 VSSQ VDDQ DQ11 DQ9 UDQS DQ10 VDDQ VSSQ VDDQ UDM DQ8 VSSQ VDD VSS VSSQ DQ0 LDM VSSQ VDDQ VDDQ DQ2 LDQS DQ1 DQ3 VSSQ VSSQ DQ6 LDQS# VDD VSS VSSQ VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 NC A8 VSS C D E F G H J K L M N P R T Notes: CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 1. Ball descriptions listed in Table 4 (page 22) are listed as “x16.” 2. A comma separates the configuration; a slash defines a selectable function. 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions Symbol Type Description A[14:13], A12/BC#, A11, A10/AP, A[9:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See Truth Table - Command. BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. DM Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8 device. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and deassertion are asynchronous. DQ[3:0] I/O CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued) Symbol Type DQ[7:0] I/O Description Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. TDQS, TDQS# I/O Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. VDD Supply Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation. VDDQ Supply DQ power supply: 1.35V, 1.283–1.45V operational; compatible with 1.5V operation. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (including self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ Reference External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. NC – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). NF – No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA – x16 Ball Descriptions Symbol Type Description A13, A12/BC#, A11, A10/AP, A[9:0] Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). See Truth Table - Command. BA[2:0] Input Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (LDQS, LDQS#, UDQS, UDQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. LDM Input Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and LDQS balls. LDM is referenced to VREFDQ. ODT Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. RESET# Input Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and deassertion are asynchronous. CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued) Symbol Type Description UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte input data is masked when UDM is sampled HIGH along with the input data during a write access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and UDQS balls. UDM is referenced to VREFDQ. DQ[7:0] I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ. DQ[15:8] I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ. LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. LDQS is center-aligned to write data. UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. UDQS is center-aligned to write data. VDD Supply Power supply: 1.35V, 1.283–1.45V operational; compatible to 1.5V operation. VDDQ Supply DQ power supply: 1.35V, 1.283–1.45V operational; compatible with 1.5V operation. VREFCA Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data: VREFDQ must be maintained at all times (including self refresh) for proper device operation. VSS Supply Ground. VSSQ Supply DQ ground: Isolated on the device for improved noise immunity. ZQ NC CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN Reference External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Package Dimensions Package Dimensions Figure 8: 78-Ball FBGA – x4, x8 (DA) 0.155 Seating plane 78X Ø0.45 Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. 1.8 CTR Nonconductive overmold 0.12 A A Ball A1 ID 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N 10.5 ±0.1 9.6 CTR 0.8 TYP 1.1 ±0.1 0.8 TYP 6.4 CTR 0.25 MIN 8 ±0.1 Notes: CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Package Dimensions Figure 9: 96-Ball FBGA – x16 (JT) 0.155 Seating plane A 1.8 CTR Nonconductive overmold 96X Ø0.45 Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. 0.12 A Ball A1 ID 9 8 7 3 2 Ball A1 ID 1 A B C D E F 14 ±0.1 G H 12 CTR J K L M N P R 0.8 TYP T 1.1 ±0.1 0.8 TYP 6.4 CTR 0.25 MIN 8 ±0.1 Notes: CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications Electrical Specifications Table 5: Input/Output Capacitance Capacitance Parameters Symbol DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 Min Max Min Max Min Max Min Max Min Max Units Single-end I/O: DQ, DM CIO 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pF Differential I/O: DQS, DQS#, TDQS, TDQS# CIO 1.5 2.5 1.5 2.5 1.5 2.3 1.5 2.2 1.5 2.1 pF Inputs (CTRL, CMD,ADDR) CI 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 pF Table 6: DC Electrical Characteristics and Operating Conditions – 1.35V Operation All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Units Notes Supply voltage VDD 1.283 1.35 1.45 V 1, 2, 3, 4 I/O supply voltage VDDQ 1.283 1.35 1.45 V 1, 2, 3, 4 Notes: 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very long period of time (for example, 1 sec). 2. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 3. Under these supply voltages, the device operates to this DDR3L specification. 4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation (see Figure 47 (page 141)). Table 7: DC Electrical Characteristics and Operating Conditions – 1.5V Operation All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Units Notes Supply voltage VDD 1.425 1.5 1.575 V 1, 2, 3 I/O supply voltage VDDQ 1.425 1.5 1.575 V 1, 2, 3 Notes: CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 1. If the minimum limit is exceeded, input levels shall be governed by DDR3L specifications. 2. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifications under the same speed timings as defined for this device. 3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation (see Figure 47 (page 141)). 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications Table 8: Input Switching Conditions – Command and Address Parameter/Condition Input high AC voltage: Logic 1 Symbol VIH(AC160)min DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866 Units 1 160 160 – mV 1 Input high AC voltage: Logic 1 VIH(AC135)min 135 135 135 mV Input high AC voltage: Logic 1 VIH(AC125)min1 – – 125 mV Input high DC voltage: Logic 1 VIH(DC90)min 90 90 90 mV Input low DC voltage: Logic 0 VIL(DC90)min –90 –90 –90 mV 1 Input low AC voltage: Logic 0 VIL(AC125)min – – –125 mV Input low AC voltage: Logic 0 VIL(AC135)min1 –135 –135 –135 mV Input low AC voltage: Logic 0 1 –160 –160 – mV Note: VIL(AC160)min 1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3L-800, two input AC levels are defined: VIH(AC160),min and VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDRL-800, the address/ command inputs must use either VIH(AC160),min with tIS(AC160) of 215ps or VIH(AC135),min with tIS(AC135) of 365ps; independently, the data inputs may use either VIH(AC160),min or VIH(AC135),min. Table 9: Input Switching Conditions – DQ and DM Parameter/Condition DDR3L-800/1066 DDR3L-1333/1600 Input high AC voltage: Logic 1 VIH(AC160)min 1 DDR3L-1866 Units 160 Input high AC voltage: Logic 1 VIH(AC135)min1 135 160 – mV 135 135 Input high AC voltage: Logic 1 VIH(AC130)min 1 mV – – 130 mV Input high DC voltage: Logic 1 VIH(DC90)min 90 90 90 mV Input low DC voltage: Logic 0 VIL(DC90)min –90 –90 –90 mV Input low AC voltage: Logic 0 VIL(AC130)min1 – – –130 mV Input low AC voltage: Logic 0 VIL(AC135)min1 –135 –135 –135 mV Input low AC voltage: Logic 0 1 –160 –160 – mV Note: Symbol VIL(AC160)min 1. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3L-800, two input AC levels are defined: VIH(AC160),min and VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDRL-800, the data inputs must use either VIH(AC160),min with tIS(AC160) of 90ps or VIH(AC135),min with tIS(AC135) of 140ps; independently, the address/command inputs may use either VIH(AC160),min or VIH(AC135),min. CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications Table 10: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) Parameter/Condition Symbol Min Max Units Differential input logic high – slew VIH,diff(AC)slew 180 N/A mV Differential input logic low – slew VIL,diff(AC)slew N/A –180 mV Differential input logic high VIH,diff(AC) 2 × (VIH(AC) - VREF) VDD/VDDQ mV Differential input logic low VIL,diff(AC) VSS/VSSQ 2 × (VIL(AC) - VREF) mV VSEH VDDQ/2 + 160 VDDQ mV Single-ended high level for strobes Single-ended high level for CK, CK# Single-ended low level for strobes VSEL Single-ended low level for CK, CK# VDD/2 + 160 VDD mV VSSQ VDDQ/2 - 160 mV VSS VDD/2 - 160 mV Table 11: Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback DDR3L-800/1066/1333/1600 tDVAC tDVAC DDR3L-1866 tDVAC tDVAC tDVAC Slew Rate (V/ns) at 320mV (ps) at 270mV (ps) at 270mV (ps) at 250mV (ps) at 260mV (ps) >4.0 189 201 163 168 176 4.0 189 201 163 168 176 3.0 162 179 140 147 154 2.0 109 134 95 105 111 1.8 91 119 80 91 97 1.6 69 100 62 74 78 1.4 40 76 37 52 55 1.2 Note1 44 5 22 24 1.0 Note1 Note1 Note1 Note1 Note1 2.0 200 213 200 205 2.0 200 213 200 205 1.5 173 190 178 184 1.0 120 145 133 143 0.9 102 130 118 129 0.8 80 111 99 111 0.7 51 87 75 89 0.6 13 55 43 59 0.5 Note 1 10 Note 1 18 2.0 165 113 95 2.0 165 113 95 1.5 138 90 73 1.0 85 45 30 0.9 67 30 16 0.8 45 11 Note1 0.7 16 Note1 – 0.6 Note1 Note1 – 0.5 Note1 Note1 – 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B must be derated by 2%; IDD2Px must be derated by 30%. CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Electrical Specifications – DC and AC DC Operating Conditions Table 41: DDR3L 1.35V DC Electrical Characteristics and Operating Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Unit Notes Supply voltage VDD 1.283 1.35 1.45 V 1–7 I/O supply voltage VDDQ 1.283 1.35 1.45 V 1–7 II –2 – 2 µA IVREF –1 – 1 µA Input leakage current Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) Notes: CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 8, 9 1. VDD and VDDQ must track one another. VDDQ must be ≤ VDD. VSS = VSSQ. 2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing parameters. 3. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very long period of time (for example, 1 second). 4. Under these supply voltages, the device operates to this DDR3L specification. 5. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 6. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifications under the same speed timings as defined for this device. 7. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation (see VDD Voltage Switching (page 141)). 8. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin should be minimal. 9. VREF (see Table 42). 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Input Operating Conditions Table 42: DDR3L 1.35V DC Electrical Characteristics and Input Conditions All voltages are referenced to VSS Parameter/Condition Symbol Min Nom Max Unit VIN low; DC/commands/address busses VIL VSS N/A See Table 43 V VIN high; DC/commands/address busses VIH See Table 43 N/A VDD V Notes Input reference voltage command/address bus VREFCA(DC) 0.49 × VDD 0.5 × VDD 0.51 × VDD V 1, 2 I/O reference voltage DQ bus VREFDQ(DC) 0.49 × VDD 0.5 × VDD 0.51 × VDD V 2, 3 I/O reference voltage DQ bus in SELF REFRESH VREFDQ(SR) VSS 0.5 × VDD VDD V 4 VTT – 0.5 × VDDQ – V 5 Command/address termination voltage (system level, not direct DRAM input) Notes: CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (non-common mode) on VREFCA may not exceed ±1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ±2% of VREFCA(DC). 2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20 MHz in frequency. 3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (non-common mode) on VREFDQ may not exceed ±1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ±2% of VREFDQ(DC). 4. VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF REFRESH, within restrictions outlined in the SELF REFRESH section. 5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. Minimum and maximum values are system-dependent. 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Table 43: DDR3L 1.35V Input Switching Conditions - Command and Address Parameter/Condition Symbol DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866 Units Command and Address VIH(AC160),min 5 160 160 – mV VIH(AC135),min5 135 135 135 mV VIH(AC125,)min – – 125 mV VIH(DC90),min 90 90 90 mV Input low DC voltage: Logic 0 VIL(DC90),min –90 –90 –90 mV Input low AC voltage: Logic 0 VIL(AC125),min5 – – –125 mV 5 –135 –135 –135 mV 5 –160 –160 – mV Input high AC voltage: Logic 1 5 Input high DC voltage: Logic 1 VIL(AC135),min VIL(AC160),min DQ and DM Input high AC voltage: Logic 1 VIH(AC160),min5 160 160 – mV 5 135 135 135 mV 5 – – 130 mV VIH(AC135),min VIH(AC125),min Input high DC voltage: Logic 1 VIH(DC90),min 90 90 90 mV Input low DC voltage: Logic 0 VIL(DC90),min –90 –90 –90 mV Input low AC voltage: Logic 0 VIL(AC125),min5 – – –130 mV 5 –135 –135 –135 mV 5 –160 –160 – mV VIL(AC135),min VIL(AC160),min Notes: 1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC). 3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC). 4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). 5. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific speed bin, the user may choose either value for the input AC level. Whichever value is used, the associated setup time for that AC level must also be used. Additionally, one VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may be used for data inputs. For example, for DDR3-800, two input AC levels are defined: VIH(AC160),min and VIH(AC135),min (corresponding VIL(AC160),min and VIL(AC135),min). For DDR3-800, the address/ command inputs must use either VIH(AC160),min with tIS(AC160) of 210ps or VIH(AC150),min with tIS(AC135) of 365ps; independently, the data inputs must use either VIH(AC160),min with tDS(AC160) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps. CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Table 44: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#) Parameter/Condition Symbol Min Max Units Notes Differential input logic high – slew VIH,diff(AC)slew 180 N/A mV 4 Differential input logic low – slew VIL,diff(AC)slew N/A –180 mV 4 Differential input logic high VIH,diff(AC) 2 × (VIH(AC) - VREF) VDD/VDDQ mV 5 Differential input logic low VIL,diff(AC) VSS/VSSQ 2 × (VIL(AC) - VREF) mV 6 Differential input crossing voltage relative to VDD/2 for DQS, DQS#; CK, CK# VIX VREF(DC) - 150 VREF(DC) + 150 mV 5, 7, 9 Differential input crossing voltage relative to VDD/2 for CK, CK# VIX (175) VREF(DC) - 175 VREF(DC) + 175 mV 5, 7–9 VDDQ/2 + 160 VDDQ mV 5 VDD/2 + 160 VDD mV 5 VSSQ VDDQ/2 - 160 mV 6 VSS VDD/2 - 160 mV 6 Single-ended high level for strobes VSEH Single-ended high level for CK, CK# Single-ended low level for strobes Single-ended low level for CK, CK# Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN VSEL Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ. Reference is VREFCA(DC) for clock and VREFDQ(DC) for strobe. Differential input slew rate = 2 V/ns. Defines slew rate reference points, relative to input crossing voltages. Minimum DC limit is relative to single-ended signals; overshoot specifications are applicable. Maximum DC limit is relative to single-ended signals; undershoot specifications are applicable. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross. The VIX extended range (±175mV) is allowed only for the clock; this VIX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 ±250mV, and the differential slew rate of CK, CK# is greater than 3 V/ns. VIX must provide 25mV (single-ended) of the voltages separation. 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 11: DDR3L 1.35V Input Signal VDD + 0.4V Narrow pulse width Minimum VIL and VIH levels VIH MIN(AC) VIH MIN(DC) VIH(AC) VIH(DC) VIL MIN(AC) VDD VIL(DC) VIL(AC) VREF + 125/135/160mV VIH(AC) VREF + 90mV VIH(DC) VREFDQ + AC noise VREFDQ + DC error VREFDQ - DC error VREFDQ - AC noise VREF - 90mV VIL(DC) VREF - 125/135/160mV VIL(AC) 0.0V VSS VSS - 0.40V Undershoot VSS - 0.40V Narrow pulse width Note: CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN VDDQ + 0.4V Overshoot VDDQ VREF DC MAX + 1% .51 x VDD VREF = VDD/2 .49 x VDD VREF DC MIN - 1% VDD MAX 2% Total VREF DC MAX VREF DC MIN MAX 2% Total VIL MIN(DC) VIL and VIH levels with ringback 1. Numbers in diagrams reflect nominal values. 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC DDR3L 1.35V AC Overshoot/Undershoot Specification Table 45: DDR3L Control and Address Pins DDR3L-800 DRR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 Maximum peak amplitude allowed for overshoot area (see Figure 12) Parameter 0.4V 0.4V 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 13) 0.4V 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above VDD (see Figure 12) 0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.28 Vns Maximum undershoot area below VSS (see Figure 13) 0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns 0.28 Vns Table 46: DDR3L 1.35V Clock, Data, Strobe, and Mask Pins Parameter DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866 Maximum peak amplitude allowed for overshoot area (see Figure 12) 0.4V 0.4V 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 13) 0.4V 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above VDD/VDDQ (see Figure 12) 0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.11 Vns Maximum undershoot area below VSS/VSSQ (see Figure 13) 0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns 0.11 Vns Figure 12: Overshoot Maximum amplitude Volts (V) Overshoot area VDD/VDDQ Time (ns) CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 13: Undershoot VSS/VSSQ Volts (V) Undershoot area Maximum amplitude Time (ns) CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 14: VIX for Differential Signals VDD, VDDQ VDD, VDDQ CK#, DQS# CK#, DQS# X VIX VIX VDD/2, VDDQ/2 X X VDD/2, VDDQ/2 VIX X VIX CK, DQS CK, DQS VSS, VSSQ VSS, VSSQ Figure 15: Single-Ended Requirements for Differential Signals VDD or VDDQ VSEH,min VDD/2 or VDDQ/2 VSEH CK or DQS VSEL,max VSEL VSS or VSSQ CCMTD-1725822587-7895 2Gb_DDR3L.pdf - Rev. O 09/18 EN 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 2Gb: x4, x8, x16 DDR3L SDRAM Electrical Specifications – DC and AC Figure 16: Definition of Differential AC-Swing and tDVAC tDVAC VIH,diff(AC)min VIH,diff,min CK - CK# DQS - DQS# 0.0 VIL,diff,max VIL,diff(AC)max tDVAC Half cycle Table 47: DDR3L 1.35V - Minimum Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback DDR3L-800/1066/1333/1600 tDVAC tDVAC DDR3L-1866 tDVAC tDVAC tDVAC Slew Rate (V/ns) at 320mV (ps) at 270mV (ps) at 270mV (ps) at 250mV (ps) at 260mV (ps) >4.0 189 201 163 168 176 4.0 189 201 163 168 176 3.0 162 179 140 147 154 2.0 109 134 95 105 111 1.8 91 119 80 91 97 1.6 69 100 62 74 78 1.4 40 76 37 52 55 1.2 Note1 44 5 22 24 1.0 Note1